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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
oki semiconductor fedd56v62162j-01 issue date: jan. 30, 2007 md56v62162j 4-bank 1,048,576-word 16-bit synchronous dynamic ram 1/36 description the md56v62162j is a 4-bank 1,048,576-word 16-bit synchronous dynamic. the device operates at 3.3 v. the inputs and outputs are lvttl compatible. features ? silicon gate, quadruple polysilicon cmos, 1-transistor memory cell ? 4-bank 1,048,576-word 16-bit configuration ? single 3.3 v power supply, 0.3 v tolerance ? input : lvttl compatible ? output : lvttl compatible ? refresh : 4096 cycles/64 ms ? programmable data transfer mode - cas latency (2, 3) - burst length (1, 2, 4, 8, full page) - data scramble (sequential, interleave) ? a uto-refresh, self-refresh capability ? packages: 54-pin 400 mil plastic tsop (typeii) ( tsop(2)54-p-400-0.80-k ) (product: md56v62162j-xxta) xx indicates speed rank. product family access time (max.) family max. frequency t ac2 t ac3 md56v62162j-7 143 mhz 5.4 ns 5.4 ns md56v62162j-75 133 mhz 5.4 ns 5.4 ns md56v62162j-8 125 mhz 6 ns 6 ns md56v62162j-10 100 mhz 6 ns 6 ns
fedd56v62162j-01 oki semiconductor md56v62162j 2/36 pin configuration (top view) pin name function pin name function clk system clock udqm, ldqm data input/ output mask cs chip select dqi data input/ output cke clock enable v cc power supply (3.3 v) a0?a11 address v ss ground (0 v) a12, a13 bank select address v cc q data output power supply (3.3 v) ras row address strobe v ss q data output ground (0 v) cas column address strobe nc no connection we write enable note : the same power supply voltage must be provided to every v cc pin and v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin. 54-pin plastic tsop(ii) (k type) 1 2 3 4 5 9 10 11 12 13 54 53 52 51 50 46 45 44 43 42 dq1 v cc q dq3 v cc v ss dq16 v ss q dq14 v ss q v cc q dq7 v ss q dq8 dq10 v cc q nc 6 7 8 14 15 dq5 ca s v cc v ss q 19 20 21 22 23 a12 a10 a0 a1 c s 16 17 18 24 25 ra s ldqm a13 w e 49 48 47 v cc q dq12 41 40 36 35 34 33 32 v ss nc a 11 a 9 a 8 a 7 a 6 39 38 37 udqm clk cke 31 30 a 5 a2 dq6 dq4 dq2 dq15 dq13 dq11 dq9 a3 26 27 a 4 29 28 v ss v cc
fedd56v62162j-01 oki semiconductor md56v62162j 3/36 pin description clk fetches all inputs at the ?h? edge. cs disables or enables device operation by asserti ng or deactivating all inputs except clk, cke, udqm and ldqm. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be ma sked so that the subsequent clk operation is deactivated. cke should be asserted at l east one cycle prior to a new command. address row & column multiplexed. row address : ra0 ? ra11 column address : ca0 ? ca7 a13, a12 (ba0, ba1) slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. ras cas we functionality depends on the combination. fo r details, see the function truth table. udqm, ldqm masks the read data of two clocks later when udq m and ldqm are set ?h? at the ?h? edge of the clock signal. masks the write data of the same clock when udqm and ldqm are set ?h? at the ?h? edge of the clock signal. udqm controls upper byte and ldqm controls lower byte. dqi data inputs/outputs are mu ltiplexed on the same pin.
fedd56v62162j-01 oki semiconductor md56v62162j 4/36 electrical characteristics absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out ?0.5 to v cc + 0.5 v v cc supply voltage v cc , v cc q ?0.5 to 4.6 v storage temperature t stg ?55 to 150 c power dissipation p d* 1000 mw short circuit output current i os 50 ma operating temperature t opr 0 to 70 c *: ta = 25 c recommended operating conditions (voltages referenced to v ss = v ss q = 0 v) parameter symbol min. typ. max. unit power supply voltage v cc , v cc q 3.0 3.3 3.6 v input high voltage v ih 2.0 ? v cc + 0.3 (*1) v input low voltage v il ? 0.3 (*2) ? 0.8 v notes: *1. the input voltage is v cc + 2.0v when the pulse width is less than 10ns (the pulse width is with respect to the point at which v cc is applied). *2. the input voltage is v ss ? 2.0v when the pulse width is less than 10ns (the pulse width respect to the point at which v ss is applied). pin capacitance (v bias = 1.4 v, ta = 25c, f = 1 mhz) parameter symbol min. max. unit input capacitance (clk) c clk ? 4 pf input capacitance ( ras , cas , we , cs , cke, udqm, ldqm, a0 - a13) c in ? 5 pf input/output capacitance (dq1 ? dq16) c out ? 6.5 pf
fedd56v62162j-01 oki semiconductor md56v62162j 5/36 dc characteristics (1/2) md56v62162 condition j-7 j-75 parameter symbol bank cke others min. max. min. max. unit note output high voltage v oh ? ? i oh = ? 2.0ma 2.4 ? 2.4 ? v output low voltage v ol ? ? i ol = 2.0ma ? 0.4 ? 0.4 v input leakage current i li ? ? ? ? 10 10 ? 10 10 a output leakage current i lo ? ? ? ? 10 10 ? 10 10 a average power supply current (operating) i cc1 one bank active cke v ih t cc = min. t rc = min. no burst ? 100 ? 90 ma 1,2 power supply current (standby) i cc2 both banks precharge cke v ih t cc = min. ? 40 ? 35 ma 3 average power supply current (clock suspension) i cc3s both banks active cke v il t cc = min. ? 3 ? 3 ma 2 average power supply current (active standby) i cc3 one bank active cke v ih t cc = min. ? 45 ? 40 ma 3 power supply current (burst) i cc4 both banks active cke v ih t cc = min. ? 140 ? 130 ma 1,2 power supply current (auto-refresh) i cc5 one bank active cke v ih t cc = min. t rc = min. ? 140 ? 130 ma 2 average power supply current (self-refresh) i cc6 both banks precharge cke v il t cc = min. ? 2 ? 2 ma average power supply current (power down) i cc7 both banks precharge cke v il t cc = min. ? 2 ? 2 ma notes: 1. measured with outputs open. 2. the address and data can be changed once or left unchanged during one cycle. 3. the address and data can be changed once or left unchanged during two cycles. dc
fedd56v62162j-01 oki semiconductor md56v62162j 6/36 dc characteristics (2/2) md56v62162 condition j-8 j-10 parameter symbol bank cke others min. max. min. max. unit note output high voltage v oh ? ? i oh = ? 2.0ma 2.4 ? 2.4 ? v output low voltage v ol ? ? i ol = 2.0ma ? 0.4 ? 0.4 v input leakage current i li ? ? ? ? 10 10 ? 10 10 a output leakage current i lo ? ? ? ? 10 10 ? 10 10 a average power supply current (operating) i cc1 one bank active cke v ih t cc = min. t rc = min. no burst ? 85 ? 70 ma 1,2 power supply current (standby) i cc2 both banks precharge cke v ih t cc = min. ? 35 ? 30 ma 3 average power supply current (clock suspension) i cc3s both banks active cke v il t cc = min. ? 3 ? 3 ma 2 average power supply current (active standby) i cc3 one bank active cke v ih t cc = min. ? 40 ? 35 ma 3 power supply current (burst) i cc4 both banks active cke v ih t cc = min. ? 125 ? 100 ma 1,2 power supply current (auto-refresh) i cc5 one bank active cke v ih t cc = min. t rc = min. ? 125 ? 100 ma 2 average power supply current (self-refresh) i cc6 both banks precharge cke v il t cc = min. ? 2 ? 2 ma average power supply current (power down) i cc7 both banks precharge cke v il t cc = min. ? 2 ? 2 ma notes: 1. measured with outputs open. 2. the address and data can be changed once or left unchanged during one cycle. 3. the address and data can be changed once or left unchanged during two cycles.
fedd56v62162j-01 oki semiconductor md56v62162j 7/36 mode set address keys single write cas latency burst type burst length a9 brsw a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 0 normal 0 0 0 reserved 0 sequential 000 1 1 1 single write 0 0 1 reserved 1 interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 full page reserved notes: a7, a8, a10, a11, a12 and a13 should stay ?l? during mode set cycle. md56v62162j supports two methods of power on sequence. power on sequence 1 1. with inputs in nop state and attempt to mainta in cke=?h?, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply an auto-refresh eight or more times. 5. enter the mode register setting command. power on sequence 2 1. with inputs in nop state and attempt to mainta in cke=?h?, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. enter the mode register setting command. 5. apply an auto-refresh eight or more times.
fedd56v62162j-01 oki semiconductor md56v62162j 8/36 ac characteristics (1/4) note1, 2 md56v62162 j-7 j-75 parameter symbol min. max. min. max. unit note cl = 3 t cc3 7 ? 7.5 ? ns clock cycle time cl = 2 t cc2 10 ? 10 ? ns cl = 3 t ac3 ? 5.4 ? 5.4 ns 3, 4 access time from clock cl = 2 t ac2 ? 5.4 ? 5.4 ns 3, 4 clock high pulse time t ch 2 ? 2.5 ? ns 4 clock low pulse time t cl 2 ? 2.5 ? ns 4 input setup time t si 1.5 ? 1.5 ? ns input hold time t hi 0.8 ? 0.8 ? ns output low impedance time from clock t olz 1 ? 1 ? ns output high impedance time from clock t ohz ? 5.4 ? 5.4 ns output hold from clock t oh 2.5 ? 3 ? ns 3 random read or write cycle time t rc 62 ? 65 ? ns ras precharge time t rp 20 ? 20 ? ns ras pulse width t ras 42 100,000 45 100,000 ns ras to cas delay time t rcd 20 ? 20 ? ns write recovery time t wr 10 ? 10 ? ns ras to cas bank active delay time t rrd 10 ? 15 ? ns refresh time t ref ? 64 ? 64 ms power-down exit setup time t pde t si +1clk ? t si +1clk ? ns cas to cas delay time (min.) l ccd 1 1 cycle clock disable time from cke l cke 1 1 cycle data output high impedance time from udqm, ldqm l doz 2 2 cycle dada input mask time from udqm, ldqm l dod 0 0 cycle
fedd56v62162j-01 oki semiconductor md56v62162j 9/36 ac characteristics (2/4) note1, 2 md56v62162 j-7 j-75 parameter symbol min. max. min. max. unit note data input mask time from write command l dwd 0 0 cycle data output high impedance time from precharge command l roh cl cl cycle active command input time from mode register set command input (min.) l mrd 2 2 cycle write command input time from output l owd 2 2 cycle
fedd56v62162j-01 oki semiconductor md56v62162j 10/36 ac characteristics (3/4) note1, 2 md56v62162 j-8 j-10 parameter symbol min. max. min. max. unit note cl = 3 t cc3 8 ? 10 ? ns clock cycle time cl = 2 t cc2 10 ? 10 ? ns cl = 3 t ac3 ? 6 ? 6 ns 3, 4 access time from clock cl = 2 t ac2 ? 6 ? 6 ns 3, 4 clock high pulse time t ch 3 ? 3 ? ns 4 clock low pulse time t cl 3 ? 3 ? ns 4 input setup time t si 2 ? 2 ? ns input hold time t hi 1 ? 1 ? ns output low impedance time from clock t olz 1 ? 1 ? ns output high impedance time from clock t ohz ? 6 ? 6 ns output hold from clock t oh 3 ? 3 ? ns 3 random read or write cycle time t rc 70 ? 70 ? ns ras precharge time t rp 20 ? 20 ? ns ras pulse width t ras 48 100,000 50 100,000 ns ras to cas delay time t rcd 20 ? 20 ? ns write recovery time t wr 10 ? 10 ? ns ras to cas bank active delay time t rrd 20 ? 20 ? ns refresh time t ref ? 64 ? 64 ms power-down exit setup time t pde t si +1clk ? t si +1clk ? ns cas to cas delay time (min.) l ccd 1 1 cycle clock disable time from cke l cke 1 1 cycle data output high impedance time from udqm, ldqm l doz 2 2 cycle dada input mask time from udqm, ldqm l dod 0 0 cycle
fedd56v62162j-01 oki semiconductor md56v62162j 11/36 ac characteristics (4/4) note1, 2 md56v62162 j-8 j-10 parameter symbol min. max. min. max. unit note data input mask time from write command l dwd 0 0 cycle data output high impedance time from precharge command l roh cl cl cycle active command input time from mode register set command input (min.) l mrd 2 2 cycle write command input time from output l owd 2 2 cycle notes: 1. ac measurements assume that t t = 1 ns. 2. the reference level for timing of input signals is 1.4 v. the input signal conditions are below. v ih = 2.4 v, v il = 0.4 v 3. output load. 4. the access time is defined at 1.4 v. 5. if t t is longer than 1 ns, then the reference level for timing of input signals is v ih and v il . output z=50 ? 30pf (external load)
fedd56v62162j-01 oki semiconductor md56v62162j 12/36 timing chart read & write cycle (same bank) @ cas latency = 2, burst length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm t oh ra ca0 t rp t rc qa1 cb0 rb rb ra qa0 qa2 qa3 db0 db1 db2 db3 t ac t oh row active read command prechar g e command row active write command prechar g e command t rcd
fedd56v62162j-01 oki semiconductor md56v62162j 13/36 single bit read-write-read cycle (same page) @ cas latency = 2, burst length = 4 clk cke c s r as c as a ddr a 12. a 13 a 10 dq we udqm, ld q m row active 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t olz db t si qc t hi qa t oh ra l owd bs bs bs bs bs ra cc cb ca t ohz t ac t hi t si t si t hi t hi t si t si t hi t hi t si i ccd t si t cl t cc t ch read command write command read command prechar g e command
fedd56v62162j-01 oki semiconductor md56v62162j 14/36 *notes: 1. when cs is set ?high? at a clock transition from ?l ow? to ?high?, all inputs except clk, cke, udqm and ldqm are invalid. 2. when issuing an active, read or write co mmand, the bank is selected by a12 and a13. a12 a13 active, read or write 0 0 bank a 0 1 bank b 1 0 bank c 1 1 bank d 3. the auto precharge function is enabled or disabled by the a10 input when the read or write command is issued. a10 a12 a13 operation 0 0 0 after the end of burst, bank a holds the idle status. 1 0 0 after the end of burst, bank a is precharged automatically. 0 0 1 after the end of burst, bank b holds the idle status. 1 0 1 after the end of burst, bank b is precharged automatically. 0 1 0 after the end of burst, bank c holds the idle status. 1 1 0 after the end of burst, bank c is precharged automatically. 0 1 1 after the end of burst, bank d holds the idle status. 1 1 1 after the end of burst, bank d is precharged automatically. 4. when issuing a precharge command, the bank to be precharged is selected by the a12 and a13 inputs. a10 a12 a13 operation 0 0 0 bank a is precharged. 0 0 1 bank b is precharged. 0 1 0 bank c is precharged. 0 1 1 bank d is precharged. 1 x x all banks are precharged. 5. the input data and the write command are la tched by the same clock (write latency = 0). 6. the output is forced to high impedance by (1clk+ t ohz ) after udqm, ldqm entry.
fedd56v62162j-01 oki semiconductor md56v62162j 15/36 page read & write cycle (same bank) @ cas latency = 2, burst length = 4 *notes: 1. to write data before a burst read ends, udqm and ldqm should be asserted three cycles prior to the write command to avoid bus contention. 2. to assert row precharge before a burst write ends, wait t wr after the last write data input. input data during the precharge input cycle will be masked internally. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm read command read command write command write command prechar g e command qa0 qa1 qb0 qb1 dc0 dc1 dd0 cc0 cd0 ca0 cb0 t wr i ccd ? note 2 ? note 1 bank a active l owd high
fedd56v62162j-01 oki semiconductor md56v62162j 16/36 burst read & single write cycle (same bank) @ cas latency = 2, burst length = 4 *note: 1. if you set a9 to high during mode register set cycle, the write burst length is set to 1. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm t oh ra ca0 qa1 cc0 cb0 ra qa0 qa2 qa3 qc0 qc1 qc2 qc3 t ac t oh row active read command write command read command prechar g e command t rcd db0 bs bs bs bs ? note 1
fedd56v62162j-01 oki semiconductor md56v62162j 17/36 read & write cycle with auto precharge @ burst length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as a ddr a 12, a 13 a 10 we a -bank prechar g e start row active (b-bank) a bank read with auto precharge b bank write with auto precharge b bank precharge start point a -bank prechar g e start high ra t rrd t wr rb ra rb ca cb db0 db1 db2 db3 qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 c as latenc y =2 c as latenc y =3 row active (a-bank) dq dq udqm, ldqm udqm, ldqm
fedd56v62162j-01 oki semiconductor md56v62162j 18/36 bank interleave rand om row read cycle @ cas latency = 2, burst length = 4 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb rac cac raa rbb rac qaa0 qaa1 qaa2 qaa3 qbb1 qbb2 qbb 3 qbb4 qac0 qac1 qac2 qac 3 row active (a-bank) read command (a-bank) precharge command (a-bank) row active (b-bank) read command (b-bank) precharge command (b-bank) row active (a-bank) read command (a-bank) t rrd t rc high
fedd56v62162j-01 oki semiconductor md56v62162j 19/36 bank interleave random row write cycle @ cas latency = 2, burst length = 4 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb rac cac raa rbb rac daa0 daa1 daa2 daa3 row active (a-bank) write command (a-bank) precharge command (a-bank) row active (b-bank) write command (b-bank) precharge command (b-bank) row active (a-bank) write command (a-bank) dbb0 dbb1 dbb2 dbb3 dac0 dac1 high precharge command (a-bank)
fedd56v62162j-01 oki semiconductor md56v62162j 20/36 bank interleave page read cycle @ cas latency = 2, burst length = 4 *note: 1. cs is ignored when ras , cas and we are high at the same cycle. clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb cac cbd cae raa rbb qaa 0 qaa1 qaa2 qaa3 qbb 0 qbb1 qbb2 qbb 3 qac0 qac1 qbd0 qbd1 qae 0 qae1 ? note 1 row active (a-bank) read command (a-bank) row active (b-bank) read command (b-bank) precharge command (a-bank) read command (a-bank) read command (a-bank) read command (b-bank) i roh high
fedd56v62162j-01 oki semiconductor md56v62162j 21/36 bank interleave page write cycle @ cas latency = 2, burst length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm row active (a-bank) row active (b-bank) write command (a-bank) precharge command (both bank) high raa caa raa rbb rbb cbd daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dbd0 write command (b-bank) write command (a-bank) write command (b-bank) daa2 daa1 daa0 cac cbb
fedd56v62162j-01 oki semiconductor md56v62162j 22/36 bank interleave random row read/write cycle @ cas latency = 2, burst length = 4 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb rac cac raa rbb rac qaa0 qaa1 qaa2 qaa3 qbb 0 qbb1 qbb2 qbb3 qac0 qac1 qac2 qac3 row active (a-bank) read command (a-bank) precharge command (a-bank) row active (b-bank) write command (b-bank) row active (a-bank) read command (a-bank) high
fedd56v62162j-01 oki semiconductor md56v62162j 23/36 bank interleave page read/write cycle @ cas latency = 2, burst length = 4 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 caa0 cbb0 cac0 qaa0 qaa1 qaa2 qaa3 read command (a-bank) write command (b-bank) read command (a-bank) dbb0 dbb1 dbb2 dbb3 qac0 qac1 high qac2 qac3
fedd56v62162j-01 oki semiconductor md56v62162j 24/36 clock suspension & dqm operation cycle @ cas latency = 2, burst length = 4 *note: 1. when clock suspension is asse rted, the next clock cycle is ignored. 2. when udqm and ldqm are asserted, the r ead data after two clock cycles is masked. 3. when udqm and ldqm are asserted, the write data in the same clock cycle is masked. 4. when ldqm is set high, the input/output data of dq1 ? dq8 is masked. 5. when udqm is set high, the input/output data of dq9 ? dq16 is masked. clk cke c s r as c as a ddr a 12, a13 a 10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra ca cb cc ra qa0 qa1 qa2 qb0 qb1 dc0 ? note 1 row active read command clock suspension read dqm clock suspension read command write command read dqm ? note 1 ? note 2 ?
fedd56v62162j-01 oki semiconductor md56v62162j 25/36 read to write cycle (same bank) @ cas latency = 2, burst length = 4 *note: 1. in case cas latency is 3, read can be interrupted by write. the minimum command interval is [burst length + 1] cycles. udqm, ldqm must be high at least 3 clocks prior to the write command. clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra ca0 cb0 ra db0 db1 ? note 1 row active read command write command precharge command t wr t rcd db2 db3 da0
fedd56v62162j-01 oki semiconductor md56v62162j 26/36 read interruption by precharge command @burst length = 8 *note: 1. if row precharge is asserted before a burs t read ends, then the read data will not output after l roh equals cas latency. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke c s r as c as a ddr a 12, a 13 a 10 we cas latenc y =2 cas latenc y =3 ra ca ra ? ?
fedd56v62162j-01 oki semiconductor md56v62162j 27/36 burst stop command @burst length = 8 clk cke c s r as c as a ddr a 12, a 13 a 10 we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cas latenc y = 2 cas latenc y = 3 qa0 qa1 qa2 qa3 qa4 qa0 qa1 qa2 qa3 qa4 read command cb qb0 qb1 qb2 qb3 qb4 qb0 qb1 qb2 qb3 qb4 burst stop command write command burst stop command high ca dq dq udqm, ldqm udqm, ldqm
fedd56v62162j-01 oki semiconductor md56v62162j 28/36 power down mode @ cas latency = 2, burst length = 4 *note: 1. when both banks are in precharge state, and if cke is set low, then the md56v62162j enters power-down mode and maintains the mode while cke is low. 2. to release the circuit from power-down mode, cke has to be set high for longer than t pde (t si + 1clk). clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra ca ra qa0 qa1 qa2 ? note 2 power-down entry row active power-down exit precharge command read command clock suspension exit t si ? note 1 clock suspension entry t pde t si t si t ref (min.)
fedd56v62162j-01 oki semiconductor md56v62162j 29/36 self refresh cycle 0 1 2 clk cke c s r as c as a ddr a 12, a 13 a 10 dq we udqm, ld q m ra bs ra self refresh entry self refresh exit row active t si t rc hi-z
fedd56v62162j-01 oki semiconductor md56v62162j 30/36 mode register set cycle auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 clk cke c s r as c a s a ddr dq we udqm, ldqm new command l mrd auto refresh t rc mrs auto refresh key ra hi - z hi - z high high 0 1 2 3 4 5 6
fedd56v62162j-01 oki semiconductor md56v62162j 31/36 function truth table (table 1) (1/2) current state 1 cs ras cas we ba addr action h x x x x x nop l h h h x x nop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra row active l l h l ba a10 nop 4 l l l h x x auto-refresh or self-refresh 5 idle l l l l l op code mode register write h x x x x x nop l h h x x x nop l h l h ba ca, a10 read l h l l ba ca, a10 write l l h h ba ra illegal 2 l l h l ba a10 precharge row active l l l x x x illegal h x x x x x nop (continue row active after burst ends) l h h h x x nop (continue row active after burst ends) l h h l x x term burst --> row active l h l h ba ca, a10 term burst, start new burst read 3 l h l l ba ca, a10 term burst, start new burst write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst, execute row precharge read l l l x x x illegal h x x x x x nop (continue row active after burst ends) l h h h x x nop (continue row active after burst ends) l h h l x x term burst --> row active l h l h ba ca, a10 term burst, start new burst read 3 l h l l ba ca, a10 term burst, start new burst write 3 l l h h ba ra illegal 2 l l h l ba a10 term burst, execute row precharge 3 write l l l x x x illegal h x x x x x nop (continue burst to end and enter row precharge) l h h h x x nop (continue burst to end and enter row precharge) l h h l ba x illegal 2 l h l h ba ca, a10 illegal 2 l h l l x x illegal l l h x ba ra, a10 illegal 2 read with auto precharge l l l x x x illegal h x x x x x nop (continue burst to end and enter row precharge) l h h h x x nop (continue burst to end and enter row precharge) l h h l ba x illegal 2 write with auto precharge l h l h ba ca, a10 illegal 2
fedd56v62162j-01 oki semiconductor md56v62162j 32/36 function truth table (table 1) (2/2) current state 1 cs ras cas we ba addr action l h l l x x illegal l l h x ba ra, a10 illegal 2 write with auto precharge l l l x x x illegal h x x x x x nop --> idle after t rp l h h h x x nop --> idle after t rp l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 nop 4 precharge l l l x x x illegal h x x x x x nop l h h h x x nop l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 write recovery l l l x x x illegal h x x x x x nop --> row active after t rcd l h h h x x nop --> row active after t rcd l h h l ba x illegal 2 l h l x ba ca illegal 2 l l h h ba ra illegal 2 l l h l ba a10 illegal 2 row active l l l x x x illegal h x x x x x nop --> idle after t rc l h h x x x nop --> idle after t rc l h l x x x illegal l l h x x x illegal refresh l l l x x x illegal h x x x x x nop l h h h x x nop l h h l x x illegal l h l x x x illegal mode register access l l x x x x illegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge ? notes : 1. all inputs are enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of l ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle.
fedd56v62162j-01 oki semiconductor md56v62162j 33/36 function truth table for cke (table 2) current state (n) cken-1 cken cs ras cas we addr action h x x x x x x invalid l h h x x x x exit self refresh --> abi l h l h h h x exit self refresh --> abi l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self refresh 6 l l x x x x x nop (maintain self refresh) h x x x x x x invalid l h h x x x x exit power down --> abi l h l h h h x exit power down --> abi l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal 6 power down 6 l l x x x x x nop (continue power down mode) h h x x x x x refer to table 1 h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l h l x illegal h l l l l h x enter self refresh h l l l l l x illegal all banks idle 7 (abi) l l x x x x x nop h h x x x x x refer to operations in table 1 h l x x x x x begin clock suspend next cycle l h x x x x x enable clock of next cycle any state other than listed above l l x x x x x continue clock suspension *notes : 6. if the minimum set-up time t pde is satisfied when cke transition from ?l? to ?h?, cke operates asynchronously so that a command can be in put in the same internal clock cycle. 7. power-down and self-refresh can be entered only when all the banks are in an idle state.
fedd56v62162j-01 oki semiconductor md56v62162j 34/36 package dimensions tsop(2)54-p-400-0.80-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.55 typ. 5 rev. no./last revised 1/aug. 14, 1997 notes for mounting the surface mount type package the tsop is a surface mount type package, which is very susceptible to heat in reflow mounting and humidity absorbed in storage. theref ore, before you perform reflow m ounting, contact oki?s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedd56v62162j-01 oki semiconductor md56v62162j 35/36 revision history page document no. date previous edition current edition description pedd56v62160j-01 jan. 6, 2004 ? ? preliminary first edition pedd56v62160j-02 jun. 23, 2004 1 1, 11, 12 speed ranks are reconsidered 5 5 pin capacitance min. spec are deleted fedd56v62160j-01 jan. 17, 2005 ? ? final edition fedd56v62160j-02 jun. 9, 2005 4 ? block diagram deleted fedd56v62160j-03 aug. 17, 2005 4,11 4,11 notes(recommended operating conditions) are added. output load is changed. fedd56v62160j-04 sep. 12, 2006 1, 5, 6, 8, 9, 10, 11 1, 5, 6, 8, 9, 10, 11 -6 rank deleted fedd56v62162j-01 jan. 30, 2007 ? ? part number changed
fedd56v62160j-03 oki semiconductor md56v62160j 36/36 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improp er handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and auto motive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2007 oki electric industry co., ltd.

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